This application claims priority from Korean Patent Application No. 1999-30871, filed on Jul. 28, 1999, the contents of which are herein incorporated by reference in their entirety.
The present invention relates generally to a semiconductor memory device. More specifically, the present invention is directed to a boosting circuit of a semiconductor memory device.
Referring to FIGS. 1 and 2, a conventional flash memory cell 1 comprises a current path or channel region 5 formed between a source 3 and a drain 4 on a semiconductor substrate 2. A floating gate 6 is formed on the substrate 2 between insulating layers 7 and 9, and has a predetermined thickness (e.g., approximately 100 xc3x85). A control gate 8 is formed above the floating gate 6.
Bias Voltages for Flash Memory Device Operations
Table 1 shows bias voltages for various operations of a flash memory device. As shown in Table 1, during a programming operation, a source voltage Vs, of the source region 3, and a bulk voltage Vb of the semiconductor substrate (or bulk region) 2, are grounded to 0V. A positive high program voltage Vpgm of around 10xcx9c20V is applied as a control gate voltage Vg to the control gate 8, while a drain voltage Vd of approximately 5xcx9c6V is applied to the drain region 4. Using these bias voltages, hot carriers are generated to program the flash memory cell 1. More specifically, electrons of the bulk region 2 are stored in the floating gate 6 as a result of the electric field generated by the high program voltage Vpgm being applied to the control gate 8. Meanwhile, charges supplied to the drain region 4 are accumulated, generating the hot carriers. After a flash memory cell 1 has been programmed, it will preferably have a program threshold voltage within a predetermined program voltage distribution area. As shown in FIG. 2, a threshold voltage distribution area for an xe2x80x9coffxe2x80x9d (programmed) cell ranges between approximately 6xcx9c8V.
As further shown below in Table 1, during an erasing operation, a negative high erase voltage Vera of approximately xe2x88x9210xcx9cxe2x88x9220V is applied as the control gate voltage Vg to the control gate 8 while a voltage of about 5V is applied as the bulk voltage Vb to the bulk region 2. Using these voltages, a Fowler-Nordheim (F-N) tunneling phenomenon is created to erase the flash memory cell 1. This F-N tunneling discharges the electrons accumulated in the floating gate 6, so that the flash memory cells have an erased threshold voltage within a predetermined voltage distribution area. As shown in FIG. 2, a threshold voltage distribution area for an xe2x80x9conxe2x80x9d (erased) cell ranges from approximately 0.5xcx9c2.5V (or between about 1xcx9c3V).
In a read operation, a flash memory cell with a high threshold voltage, as a result of the program operation, registers as an xe2x80x9coffxe2x80x9d cell. This is because current flow from the drain region 4 to the source region 3 is prevented. Because current is permitted to flow from the drain region 4 to the source region 3 during a read operation in a flash memory cell with a low threshold voltage, such a cell appears as an xe2x80x9conxe2x80x9d cell.
In a flash memory cell array, the flash memory cells included in one sector are simultaneously erased because they share the same bulk region 2. Due to the lack of uniformity in threshold voltages between flash memory cells, however, when all of the flash memory cells in a sector are erased at the same time, the threshold voltage of one or more of the flash memory cells often drops below the minimum desirable erased cell threshold voltage distribution level. Erased flash memory cells that have a threshold voltage of 0V or less are called xe2x80x9cover-erased memory cellsxe2x80x9d. To correct over-erased memory cells, a series of over-erase repair operations should be performed. Over-erase repair operations increase the threshold voltage of the over-erased flash memory cells to within the desired erased threshold voltage distribution area.
Referring to FIG. 3, a conventional multi-bank NOR flash memory device comprises memory cell arrays 11, 21, row decoders 13, 23, column decoders 15, 25, latch and control circuits 17, 27, an input/output (I/O) interface circuit 30, an erase control circuit 40, a program control circuit 50, a block data storage circuit 60, and a high voltage generation circuit 70. A nonmulti-bank NOR-type memory device, on the other hand, comprises only a single memory cell array, row decoder, column decoder, and latch and control circuit.
Referring to FIGS. 1, 2, and 3, in general, operation of the flash memory device is divided into program, erase, and read operations. As mentioned above, the program operation is performed by injecting electrons into the floating gate 6 using hot electrons created at a channel 5 of a memory cell 1. The erase operation is performed by discharging the electrons in the floating gate 6 to the substrate 2 using F-N tunneling. The read operation is performed by applying a wordline voltage W/L Voltage of around 3.5xcx9c5V to a control gate 8 of the memory cell 1.
It should be noted that the wordline voltage for the read operation is selected between the uppermost erased cell threshold voltage distribution level (approximately 2.5V) and the lowermost programmed cell threshold voltage distribution level (approximately 6V). The multi-bank NOR flash memory device supplies a respectively independent address to the banks 11, 21 from the I/O interface circuit 30, thereby enabling an operation such as a read while write (RWW) operation. Those skilled in the art understand the program, erase, and read operations of the multi-bank flash memory device, and a detailed description thereof will therefore be omitted.
The trend in semiconductor memory devices is toward lower operating voltages. A typical flash memory device must operate in an extremely low voltage range (e.g., below 2V or 1.7V). A high voltage generation circuit 70 uses the low operating voltage to generate the high voltages (e.g., the program voltage Vpgm, erase voltage Vera, and read voltage Vrea) supplied to the control gate 8 of the memory cell 1. This circuit 70 therefore plays an important role in the execution of the cell operations. The design and construction of the high voltage generation circuit 70 is therefore important in maintaining fast operational speeds in the NOR-type flash memory device.
Referring to FIGS. 3 and 4, a conventional high voltage generation circuit 70 comprises a program voltage generation circuit 71, an erase voltage generation circuit 73, and, a read voltage generation circuit 75. The program voltage generation circuit 71 generates a program voltage Vpgm by controlling the program control circuit 50 and the latch and control circuits 17, 27. The erase voltage generation circuit 73 generates an erase voltage Vera by controlling the erase control circuit 40 and the latch and control circuits 17, 27. The read voltage generation circuit 75 generates a read voltage Vrea by controlling the latch and control circuits 17, 27. The voltages Vpgm, Vera, and Vrea generated from the voltage generation circuits 71, 72, 73 are transferred to the row decoders 13, 23 through switching means, and are finally transferred to a word line WL selected by the row decoders 13, 23. To provide a fast operation speed, the read voltage generation circuit 75 utilizes a boosting circuit.
Referring to FIG. 5, the conventional read voltage generation circuit 75 comprises a switch S1 connected between an input terminal and two capacitors C1, CL. A precharge circuit 75a is also provided. When the precharge circuit 75a precharges a node N1 up to a power supply voltage VCC level, a boosting operation of the read voltage generation circuit (or boosting circuit) 75 starts. More specifically, when the node N1 is precharged to the power supply voltage VCC, a voltage level of the switch S1 input terminal transitions from a ground voltage VSS to the power supply voltage VCC and the switch S1 is turned on. When the power supply voltage VCC is transferred to the capacitor C1 through the switch S1, the voltage level of the node N1 is then boosted up to a predetermined level using the coupling effect of the capacitor C1. A boosted voltage (i.e., read voltage Vrea) charged to the node N1 is then transferred to a word line WL through the row decoders 13, 23 (see FIG. 3).
As noted previously, the trend in semiconductor memory devices is toward lower operating voltage levels. In fact, current NOR-type flash memory devices are operated using extremely low voltage levels (e.g., approximately 2V, 1.7V, or less). Therefore, using the boosting circuit 75 constructed as shown in FIG. 5, it is difficult to obtain a sufficient voltage level for the read voltage Vrea that is required for conducting a read operation of a memory cell. For example, assuming that the NOR flash memory device is operated using an operating voltage of 1.7V, generating a boosted voltage of 3.5V or more for the read voltage Vrea is difficult using the read voltage generation circuit 75. This is because a boosting efficiency of about 200% or more is required.
Reducing an erased threshold voltage distribution of a memory cell and/or increasing the size of the boosting capacitor have been studied and suggested as ways of solving this problem. Unfortunately, lower erased threshold voltages may result in a program/read failure caused by a drain turn-on phenomenon. And increasing the size of the boosting capacitor results in an increase in chip size. Accordingly, the implementation of these proposed methods includes a number of drawbacks.
Various embodiments of the present invention provide a boosting circuit that is able to quickly produce a boosted voltage level sufficient to operate a semiconductor memory device with a low operating voltage.
Various embodiments of the invention provide a boosting circuit that uses a low operating voltage to generate a boosted voltage sufficient to operate a semiconductor memory device while reducing an increase in area of the semiconductor memory device.
According to one aspect of the invention, a boosting unit is configured to generate a boosted voltage having a voltage level higher than a power supply voltage level. The boosting unit preferably comprises a plurality of boosting circuits connected in series. Each of the boosting circuits boosts up an input voltage in response to a boosting signal, and outputs an output voltage having a voltage level higher than that of the input voltage. Each of the boosting circuits is also provided with a corresponding enabling/disabling boosting signal. Each of the boosting circuits includes a precharge circuit, a capacitor circuit, and a switching circuit.
The precharge circuit charges a corresponding output terminal of the boosting circuit in response to a precharge signal. The capacitor circuit comprises a boosting capacitor, and has a first electrode (or terminal) and a second electrode (or terminal). The first electrode is connected to the corresponding switching circuit. The second electrode is connected to the output terminal of the corresponding precharge circuit. The switching circuit comprises a first switching transistor connected between a first power supply voltage and the first electrode of the boosting capacitor and is switched by the corresponding boosting signal. A second switching transistor is connected between a second power supply voltage and the first electrode of the boosting capacitor and is switched by the corresponding boosting signal. The switching circuit responds to a corresponding boosting signal to charge/discharge the capacitor circuit by connecting the capacitor circuit to a first or a second power supply voltage.
Alternatively, the capacitor circuit can include a first electrode connected to the corresponding switching circuit, a second electrode connected to an output terminal of the corresponding boosting circuit, and a plurality of boosting capacitors that are connected to each other in parallel. The switching circuit can include a plurality of first-type switching transistors connected between the first power supply voltage and the corresponding second voltage of the boosting capacitor. The first-type switching transistors are switched by the corresponding boosting signal. A plurality of second-type switching transistors are connected between the second power supply voltage and the corresponding first electrode of the boosting capacitor and are switched by the corresponding boosting signal.
The boosting circuit of a final terminal can include all of the components of the other boosting circuit(s) and further comprise a boosting control circuit to control a boosting efficiency of a finally outputted boosted voltage in response to a plurality of boosting selection signals. The boosting control circuit includes a current path formed between the corresponding first switch transistor and the corresponding second switch transistor, and a plurality of third switch transistors having a gate controlled by the corresponding boosting selection signal.
According to another embodiment of the invention, a boosting unit for generating a boosted voltage higher than a power supply voltage comprises a first switching circuit, a first boosting circuit, a first precharge circuit, a second switching circuit, a second boosting circuit, and a second precharge circuit. The first switching circuit selectively transfers a power supply voltage or a ground voltage in response to a first boosting signal from the outside. The first boosting circuit has a first terminal connected to an output terminal of the first switching circuit. The first precharge circuit precharges a second terminal of the first switching circuit to the power supply voltage level.
The second switching circuit selectively transfers either an output voltage or the ground voltage from the second terminal of the first boosting circuit in response to a second boosting signal. The second boosting circuit has a first terminal connected to an output terminal of the second switching circuit. The second precharge circuit precharges a second terminal of the second boosting circuit to the power supply voltage level. The first and the second boosting circuits simultaneously carry out a boosting operation in response to the first and the second boosting signals.
According to a further embodiment of the invention, a boosting unit for generating a boosted voltage having a voltage level higher than a power supply voltage comprises a plurality of boosting circuits, and a boosting control circuit for generating a plurality of boosting control signals. Each of the boosting circuits boosts up an input voltage in response to a corresponding one of a plurality of simultaneously enabled and disabled boosting signals. The boosting circuits output a plurality of output voltages, each having a voltage level higher than that of its input voltage. The boosting control signals control a final boosting circuit in response to a corresponding boosting signal and externally applied row addresses. The final boosting circuit selectively outputs a boosted voltage through an output terminal corresponding to the row addresses, in response to the boosting control signals.
Each of the boosting circuits preferably includes a precharge circuit, a capacitor circuit, and a switching circuit. The precharge circuit charges an output terminal of the corresponding boosting circuit with the precharge voltage in response to a precharge signal. The capacitor circuit is connected to the output terminal of the precharge circuit. The switching circuit connects the capacitor circuit to a first or a second power supply voltage to charge/discharge the capacitor circuit in response to the corresponding boosting signal.
In addition to these components, the boosting circuit of the final terminal further comprises a boosting control unit which controls boosting efficiency of a finally outputted boosted voltage in response to a plurality of boosting selection signals. The boosting control unit includes a plurality of boosting control circuits that output the boosting control signals in response to the boosting signal and the corresponding one of the row addresses. Each of the boosting control circuits includes a NAND gate that NANDs the boosting signal with a corresponding row address to generate an output signal, and a level shifter that supplies the boosted voltage to a corresponding boosting circuit in response to an output signal from the NAND gate.
The capacitor circuit comprises a first electrode (or terminal) of a boosting capacitor connected to the corresponding switching circuit, and a second electrode (or terminal) connected to an output terminal of the corresponding boosting circuit. The switching circuit comprises a first switching transistor which is connected between the first power supply voltage and the first electrode of the boosting capacitor and is switched by the corresponding boosting signal. A second switching transistor is connected between the second power supply voltage and the first electrode of the boosting capacitor and is switched by the corresponding boosting signal.
Alternatively, the capacitor circuit may comprise a plurality of boosting capacitors are connected in parallel between a first electrode and a second electrode of the capacitor circuit. The first electrode of the capacitor circuit is connected to the switching circuit. The second electrode is connected to an output terminal of the corresponding boosting circuit. The switching circuit comprises a plurality of first-type switching transistors that are connected between the first power supply voltage and the corresponding electrode of the boosting capacitor and are switched by the corresponding boosting signal. A plurality of second-type switching transistors are connected between the second power supply voltage and the corresponding first electrode of the boosting capacitor and are switched by the corresponding boosting signal.
Boosting circuits connected in series carry out a boosting operation at the same time, thereby generating a boosted voltage that is boosted up with the required boosting efficiency at a high speed. The final boosting circuit selectively outputs a boosted voltage through an output terminal corresponding to a row address, thereby preventing boosting efficiency from degrading as a result of the capacitance of an output terminal. This also minimizes any increase in the area of a boosting circuit.